Andrzej J. Strojwas

A. J. · A. S. · J. S.

titleISBN-13
(ISBN-10)
year of publica-
tion
other author(s)
A Unified Approach for Timing Verification and Delay Fault Testing978-0-7923-8079-5
(0-7923-8079-7)
1997Mukund Sivaraman
VLSI Design for Manufacturing: Yield Enhancement978-0-7923-9054-1
(0-7923-9054-7)
1989Stephen W. Director · Wojciech Maly

Andrzej J. Szwarc